"FinFETs: Thermal Modeling, Analysis, and Circuit Design"
Soha Hassoun

As device dimensions shrink into the nanometer range, power and performance demands prohibit the longevity of traditional MOS devices in circuit design. A finFET, a quasi-planar double-gated device, has emerged as a potential replacement. A finFET is formed by creating a silicon fin which protrudes out of the wafer, wrapping a gate around the fin, and then doping the ends of the fin to form the source and drain.

We focus in this talk on FinFET thermal and electrical issues. While finFETs provide promising electrostatic characteristics, they, like other ultra-thin body nano devices, have the potential to suffer from significant self heating. We use a thermal model to study the electro-thermal properties of multi-fin devices with both flared and rectangular channel extensions. We analyze variations in fin geometric parameters such as fin width and gate length, and we investigate the impact on thermal sensitivity using our thermal sensitivity metric, METS. We also report on gate sizing and independent gate biasing of finFET circuits. We show that finFET circuits are superior to 32nm circuits in performance, and in both dynamic and static power consumption.

Our work is novel because it provides the first thermal study of multi-fin devices and because it investigates thermally-aware finFET-based circuit design. Our thermal sensitivity metric is the first to capture device robustness to self-heating. Our finFET and 32nm bulk MOSFET circuit-level comparisons provide insight into future technologies. This work paves the way for future nanometer device and circuit-level design.

Bio:

Soha Hassoun (PhD -- University of Washington; MS -- MIT; BS -- SDSU) is currently on leave at Carbon Design Systems, Waltham, MA, focusing on system-level validation. She is an associate professor at Tufts University, Medford, MA, in the Department of Computer Science. Between her MS and PhD, Soha was a circuit designer at Digital Equipment Corp. and worked on several projects including the Alpha 21064. Soha was on leave at IBM Austin research labs in 2002. Soha is an NSF CAREER award recipient. Soha has served on the technical and executive committees for several conferences and workshops including DAC, ICCAD, IWLS, and TAU. She was the technical Program Chair for ICCAD in 2005 and the General Chair in 2006. Soha served as an associate editor for IEEE Transaction on Computer-Aided Design and currently serves as an associate editor for IEEE Design and Test. Soha was recently selected to serve on the DSSG (Defense Science Study Group), affiliated with the Institute for Defense Analyses. She has served on IEEE's CEDA (Council on Design Automation) technical activities committee since 2005. Soha severed as Director of Educational Activities for the ACM/SIGDA (Special Interest Group on Design Automation) for several years. In 2007, Soha received the ACM/SIGDA Distinguished Service award for the creation of the PhD Forum at DAC in 1997.